Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs

Abstract

Semiconductor devices with a low gate leakage current are preferred for low power application. As the devices are scaled down, sidewall spacer for CMOS transistor in nano-domain becomes increasingly critical and plays an important role in device performance evaluation. In this work, gate tunneling currents have been modeled for a nano-scale MOSFET having different high-k dielectric spacer such as SiO₂, Si₃N₄, Al₂O₃, HfO₂. The proposed model is compared and contrasted with Santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed in the results that gate leakage current decreases with the increase of dielectric constant of the device spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering and subthreshold slope of the device.