Novel hysteresis effect in ultrathin epitaxial Gd₂O₃ high-k dielectric

Abstract

Charge trapping in ultrathin high-k Gd₂O₃ dielectric leading to appearance of hysteresis in C–V curves is studied by capacitance-voltage, conductance-frequency and current-voltage techniques at different temperatures. It was shown that the large leakage current at a negative gate voltage causes the reversible trapping of the positive charge in the dielectric layer, without electrical degradation of the dielectric and dielectricsemiconductor interface. The capture cross-sections of the hole traps are around 10⁻¹⁸ and 2 × 10⁻²⁰ cm² . The respective shift of the C–V curve correlates with a “plateau” at the capacitance corresponding to weak accumulation at the silicon interface.